Such a resequencing system is already known in the art, e.g. from the article `Design and Technology Aspects of VLSI's for ATM Switches` by T. R. Banniza e.a., IEEE Journal on selected areas in communications, Vol. 9, No. 8, October 1991, pp. 1255-1264. Therein the resequencing system includes an input circuit between the buffer register and the second switching node which allocates a time stamp value provided by a time stamp generator to each of the cells applied to an input of the input circuit prior to these cells being switched by the second switching node. After this switching operation has been performed this cell is submitted by a resequencing unit to an additional variable delay which is so chosen that the total delay to which the cell is submitted between the input of the input circuit and an output of the resequencing unit becomes equal to a constant value.
The output buffer temporarily stores the cells switched by the first switching node before forwarding them to the second switching node. Such an output buffer is needed in order to avoid possible output contention occurring when different cells coming from different inputs of the first switching node are switched to the same output of the first switching node within one cell time. Due to this output buffering the cells are subjected to additional non-constant delays, i.e. the cells are subjected to delay jitter.